`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2020/07/27 13:16:53
// Design Name: 
// Module Name: hilo_reg
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module hilo_reg(
    input  wire          clk,
    input  wire          rst,
    input  wire          wr_en,
    input  wire [31:0]   hi_input,
    output reg  [31:0]   hi_o,
    input  wire [31:0]   lo_input,
    output reg  [31:0]   lo_o
    );


    always @ (posedge clk) begin
	    if (rst == `ResetEnable) begin
            lo_o <= `ZeroWord;
            hi_o <= `ZeroWord;
        end else if (wr_en == `WriteEnable) begin
			lo_o <= lo_input;
            hi_o <= hi_input;
		end
    end
endmodule